The kernel finally learned where your cache lives

😁 Hello, super humans! Yesterday we argued that your agent stack is starving the CPU, not the GPU. Today the kernel maintainers handed us a partial answer, and they have been working on it for over a year. Linux 7.2 is out, and the headline feature is a scheduler that finally cares which cache your threads are sitting next to.

📰 Quick Signals

• 🧠 AI: starting today, Microsoft splits work and personal accounts in the Copilot web, desktop and mobile apps so users stop mixing tenants by accident.
• 🤖 Robotics: the IFR puts global industrial robot installations at 542,000 units with a record market value of 16.7 billion dollars, more than double the count of a decade ago.
• 💻 Programming: GNOME 51 beta starts the freeze with 47 updated modules, web-based authentication in Shell and a Wayland protocol for blurred window backgrounds; stable is locked to September 12.
• ⚡ Electronics: DRAM contract prices are still tracking 13 to 18 percent up quarter over quarter in Q3, with NAND at 10 to 15 percent, but the consumer side has hit an affordability ceiling.
• 📡 Telecom: Deutsche Telekom is planning an open RAN rollout across roughly 30,000 sites after its Nokia swap-out went better than expected.

🔍 The Big Story: Linux 7.2 ships the scheduler fix for the CPU crunch

If you run anything latency-sensitive on a many-core server, the most important thing that happened this weekend was not a model release. It was a kernel release that changes where your threads run.

What happened: Linus Torvalds cut the stable Linux 7.2 release on August 16, closing one of the busiest development cycles in the kernel’s history at roughly 600,000 added lines. The headline is cache-aware scheduling, designed by Intel’s Tim Chen, Chen Yu and Peter Zijlstra, which finally merged after more than a year of review rounds. LWN has the technical writeup on how it works, and Phoronix tracked the tuning knob added late in the series.

The details: the Completely Fair Scheduler has historically treated your CPUs as interchangeable slots. On a modern server they are not. A dual-socket EPYC or Sapphire Rapids box has several last-level cache (LLC) domains, and moving a thread across that boundary means its warm cache lines are now on the wrong side of the interconnect. Cache-aware scheduling tracks which threads belong to the same process family and biases placement so they stay inside one LLC domain, unless load balancing genuinely demands otherwise.

flowchart LR
  subgraph before["Before: cache-blind placement"]
    direction TB
    L1["LLC domain A"] --> T1["worker 1"]
    L1 --> T2["worker 2"]
    L2["LLC domain B"] --> T3["worker 3"]
    L2 --> T4["worker 4"]
    T3 -. "cross-domain refill" .-> L1
  end
  subgraph after["Linux 7.2: cache-aware placement"]
    direction TB
    L3["LLC domain A"] --> W1["worker 1"]
    L3 --> W2["worker 2"]
    L3 --> W3["worker 3"]
    L3 --> W4["worker 4"]
    L4["LLC domain B"] --> O["other workloads"]
  end
  before --> after

The numbers are workload-dependent and the maintainers are honest about it. A ChaCha20 benchmark on AMD EPYC Genoa gained 44 percent throughput with the feature on, and latency-sensitive tests like hackbench and schbench completed up to 30 percent faster on Sapphire Rapids. Memory-bandwidth-bound and network-bound tests such as stream and netperf barely moved, and a few cases regressed slightly. That is why the feature ships behind a runtime knob rather than on by default for everyone.

The rest of 7.2 is not filler either. Btrfs turns on large folios by default after they were experimental since 6.17, so the filesystem handles memory in bigger chunks, and direct I/O no longer serializes, which reportedly lifts write performance by as much as 59 percent. On the language side, IBM’s s390 architecture joins the list of targets that can build Rust kernel code, and the tree now vendors the Rust zerocopy crate to keep low-cost memory primitives out of hand-written unsafe blocks.

🗞️ More News

🧠 AI

• Alibaba says the Qwen family has passed three billion cumulative downloads, with more than 460 open models published and over 300,000 community derivatives built on them.
• Following Saturday’s coverage, Qwen3.8-27B crossed three million Hugging Face downloads within three days of release, which is the fastest ramp the org has posted for a dense model.
• AMD and Anthropic will deploy up to 2 gigawatts of Instinct MI450 Series GPUs in Helios racks alongside EPYC Venice CPUs, with the first gigawatt starting in H1 2027 and AMD committing up to 5 billion dollars in equity.
• Google folded its AI org into one Mountain View reporting line: Demis Hassabis moved to Chairman and Koray Kavukcuoglu took operations, ending the Brain and DeepMind split.
• OpenAI published its August update notes for GPT-5.6 on the Deployment Safety Hub, the closest thing the lab offers to a changelog for behavior changes.
• OpenAI is putting frontier cyber capability models behind a vetted-access program rather than a general API tier, a pattern more labs are copying this quarter.
• OWASP researchers keep repeating the uncomfortable part: prompt injection is an architectural problem, not a filtering problem, because a model sees system prompt, user input and retrieved content as one token stream.
• OWASP’s production telemetry still puts prompt injection at the top of agentic failure modes, ahead of tool misuse and excessive agency.

🤖 Robotics

• Avatar Robotics raised a 6.5 million dollar seed round for semi-humanoid mobile manipulators plus teleoperation, and says its fleet has already handled more than 900,000 products inside live customer facilities.
• Skild picked up the Fetch Robotics assets from Zebra, buying a decade of warehouse AMR engineering to feed a general-purpose robot brain.
• Sereact closed a Series B to expand its Cortex 2.0 robot brain and open a US presence, joining the growing set of vendors selling the policy layer rather than the arm.
• Luminous raised funding to bring its LUMI solar construction robot to Australia, one of the few outdoor, unstructured deployments with a real cost case behind it.

💻 Programming

• QEMU 11.1.0 landed on August 12 with support for recent Arm CPU models and QMP monitor hot-plug, worth a look if your CI matrix emulates aarch64.
• Linux 7.2 also removed the last in-tree users of strncpy(), closing a decade-long cleanup of a function that never did what its name suggested.
• GIMP developers previewed the 3.4 feature set: a real project format, better PSD compatibility and expanded non-destructive editing.
• KDE Plasma 6.6 picks up a three-year LTS window, which finally makes it a defensible choice for a fleet of developer workstations.
• OpenSSH 10.5 shipped this week, so check your config for anything the release notes deprecate before your next fleet-wide upgrade.

⚡ Electronics

• Bloomberg calls this China’s chip breakout moment, with CXMT now the world’s fourth-largest memory maker and Huawei anchoring domestic AI hardware demand.
• CXMT is targeting domestic HBM3 mass production by the end of 2026, with Naura and Maxwell supplying assembly tooling, which would put Chinese AI accelerators on Chinese stacked memory.
• A 2 dollar RISC-V board built on the CH32V006F8U6 gives you 48 MHz, 8 KB of SRAM and 62 KB of flash, which is more than enough for a sensor node that used to need an ATtiny.
• The PULSAR C6 packs an ESP32-C6 into a compact RISC-V board with Wi-Fi 6, Bluetooth 5, Thread and Matter, aimed at people who want one radio stack instead of three.

📡 Telecom

• AT&T is running a multivendor open RAN test on its commercial network and still targets 70 percent of wireless traffic on open-capable platforms by the end of 2026, with roughly half there already.
• Nokia’s mobile boss pushed back on the obituaries, arguing open RAN is not dead even as the market consolidates toward a two-vendor reality in Europe.
• Ericsson’s AI in RAN subscription claims up to 20 percent higher downlink throughput and up to 10 percent better spectral efficiency across more than 15 live deployments.
• Following up on last week’s launch, AST SpaceMobile’s BlueBirds 11, 12 and 13 are confirmed in orbit, with the AT&T and Verizon beta still explicitly non-continuous coverage.

👨‍💻 Code Corner

Before you can reason about cache-aware scheduling, you need to know how many last-level cache domains your machine actually has. The kernel already exposes it, and almost nobody looks.

# Every distinct L3 (last-level cache) domain on this machine.
llc_domains() {
  for cpu in /sys/devices/system/cpu/cpu[0-9]*; do
    for idx in "$cpu"/cache/index*; do
      [ "$(cat "$idx/level" 2>/dev/null)" = "3" ] || continue
      cat "$idx/shared_cpu_list"
    done
  done | sort -u
}
llc_domains

# Then measure the thing the scheduler is now trying to avoid:
# the same work inside one domain versus spread across two.
one=$(llc_domains | sed -n 1p)
two=$(llc_domains | paste -sd, -)
taskset -c "$one" ./your_benchmark   # inside a single LLC
taskset -c "$two" ./your_benchmark   # spanning every LLC on the box

If the two runs differ by more than noise, your workload is cache-sensitive and Linux 7.2 has something for you.

🧰 Toolbox

• Cache Aware Scheduling on LWN: the clearest explanation of the process-family heuristic and why it took a year of review to land.
• Phoronix cache-aware balancing tracker: the v4 series coverage, including the tuning knob and the regression cases the maintainers flagged.
• hwloc and lstopo: draws your machine’s full cache, socket and NUMA topology as a picture, which beats parsing sysfs by hand.
• QEMU 11.1: fresh Arm CPU models and QMP hot-plug, useful for reproducing a topology you do not physically own.
• Qwen model org: 460-plus open models in one place, now the single largest source of open-weight downloads.
• Raspberry Pi Pico 2: the RP2350 board with two Arm cores and two Hazard3 RISC-V cores on the same die, still the cheapest way to compare the two ISAs on identical hardware.

🎬 Demo Watch (rotating)

Scalable Vision-Language-Action Model Pretraining with Real-Life Human Activity Videos

The demo: a dexterous-hand policy pretrained not on robot teleoperation logs but on ordinary video of humans doing things with their hands, then fine-tuned on a comparatively small amount of real robot data.

Why it is hard: robot action data is the bottleneck in this whole field. Teleoperation is slow, expensive and does not generalize past the rig you collected it on. Human video is essentially free and effectively infinite, but a human hand is not a gripper, the camera is not the robot’s camera, and there are no action labels anywhere in the footage. The work has to bridge that embodiment gap before any of the data is usable.

Hype versus real: the zero-shot results on unseen real-world observations are genuinely interesting, and the fine-tuned success rates on novel objects improve meaningfully. What is not true is the implied headline that you can skip robot data. You still need real demonstrations to close the loop; the pretraining just makes each one worth more. Read the success-rate tables, not the video montage.

📚 From the Blog

• Turning Pixels Into Something the AI Can Eat: how raw camera frames become tensors, and a natural companion to today’s big story since that conversion is exactly the cache-hostile CPU work a scheduler can help or ruin.
• Building Your First Neuron From Scratch: weights, bias, activation and a single gradient step, written by hand before any framework hides it.
• The Network Behind the Cameras: the unglamorous plumbing that moves video across a network without choking it.

😀 The Bot Says…

Six hundred thousand lines of kernel changes, and the marquee feature is essentially “please sit next to your friends.” Turns out the hardest problem in computing is still cache invalidation, naming things, and seating charts.

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That’s all for today! Boot 7.2 on one non-critical box, flip the knob, and reply with the delta you measure; I will publish the interesting ones.