😁 Hello, super humans! Every conversation about AI scaling eventually becomes a conversation about interconnect, and every conversation about interconnect eventually runs into a number almost nobody quotes: terabits per second per millimetre of package edge. ECOC opened in Málaga yesterday, and the demos landing today are all circling that same wall. Today we go one level below the press release and look at why the edge of a chip became the scarcest real estate in the data center.
📰 Quick Signals
- 🧠 AI: GPT-6 Astra appears to have cracked a German ADFGVX radio message from 1918 that had sat undeciphered for a century.
- 🤖 Robotics: SoftBank agreed to acquire the Robotics and AI Institute, a deal rumoured for months and now in front of the Committee on Foreign Investment in the United States.
- 💻 Programming: Java 27 shipped with G1 restored as the default garbage collector, which quietly changes the tuning advice in a decade of blog posts.
- ⚡ Electronics: Sherline is winding down manufacturing after 52 years, with the last miniature lathe and mill expected off the line by the end of October.
- 📡 Telecom: Coherent opened ECOC with PhotonLink, an integrated optics platform pitched at co-packaged, near-packaged and chip-to-chip connectivity in one family.
The Big Story: The chip ran out of edge to talk through
If you have ever wondered why the AI infrastructure story keeps turning into an optics story, today is the clearest illustration yet. The constraint is not transistors and it is not fiber in the ground. It is the perimeter of a package.
What happened: At ECOC 2026 in Málaga, Lumentum announced a joint demonstration with Qualcomm Technologies and Corning of an optical die-to-die interconnect for AI scale-up. The board-level build pairs a Qualcomm die-to-die interface IP subsystem with a Lumentum optical engine based on 1060 nm vertical-cavity surface-emitting lasers, and Corning multimode fiber ferrules doing the connectivity. The point is not a product launch; it is a proof that a die-to-die interface of the kind normally reserved for millimetres of substrate, UCIe included, can be driven straight onto fiber and carried tens of metres.
The details: Here is the number that matters. Shoreline bandwidth density is how much traffic you can get through one millimetre of the chip’s edge, and it is the ceiling nobody can design around, because the edge does not grow when the die does. The demo is built from optical channels running a deliberately unglamorous 32 Gb/s NRZ each, and the architecture is claimed at roughly 1 Tb/s per millimetre of shoreline today with a line of sight to about 4 Tb/s per millimetre as lane rates and channel counts climb. The optical engine itself carries around 10 Tb/s of aggregate transmit and receive capacity using two-dimensional VCSEL and photodetector arrays with backside lens technology, built on the same high-volume line that makes 3D sensing modules for phones. Note the strategy: rather than chase exotic per-lane speeds, you go massively parallel and cheap per lane, which is exactly how VCSEL links have always won.
flowchart LR
subgraph E["Electrical D2D today"]
A1["Die A"] -->|"SerDes + package traces"| A2["Die B"]
A2 -.->|"reach: millimetres to ~1 m"| A3["wall: shoreline density + power"]
end
subgraph O["Optical D2D demo"]
B1["Die A + D2D IP"] --> B2["1060 nm VCSEL engine"]
B2 -->|"multimode fiber"| B3["photodiode array"]
B3 --> B4["Die B + D2D IP"]
B4 -.->|"reach: tens of metres"| B5["scale-up domain grows"]
end
The reach number is the part with architectural consequences. A scale-up domain today is roughly “how many accelerators can I reach with copper before signal integrity and power give up”, which is why a rack is the natural unit. Push die-to-die semantics out to tens of metres at comparable latency and power, and the natural unit becomes a row. That is a different machine, not a faster version of the same one.
Important
Our take: Treat the 32 Gb/s NRZ figure as the honest part of this announcement, not the weak part. Everyone demoing 448 Gb/s PAM4 front ends this week is solving a different problem, and per-lane heroics buy you bandwidth at the cost of DSP, power and latency. Going wide with boring lanes is how you keep the energy per bit low enough that the link can live next to the compute instead of on the far side of a retimer. What I would actually watch is not the terabits, it is the connector and the assembly yield: Corning’s ferrules are in this demo because fiber alignment at package density is the thing that has killed every previous attempt to move optics onto the substrate. Also worth saying plainly: this is a proof of concept on a board at a trade show, and the gap between that and a shippable co-packaged part has historically been measured in years.
🗞️ More News
🧠 AI
- Google, Anthropic and OpenAI all rolled out cyber-focused models, safeguards and access programmes within days of each other, including Gemini 3.8 Flash Cyber for autonomous vulnerability discovery.
- Vortex pairs vector quantization with input-dependent sparsity and targets systolic-array accelerators directly, which is the rare compression paper written for the hardware people actually deploy on.
- Nvidia extended its data center roadmap to 2028 after the LPU launch at GTC, with Vera, Rubin, NVLink Switch and BlueField-4 all landing in the same planning window.
- LibreOffice 26.8 set a download record while the Document Foundation leaned into “no AI” as a headline feature, which is a data point about user appetite rather than about the software.
- A dispute over AI contribution policy left 113 Void Linux packages orphaned, a reminder that maintainer goodwill is a dependency with no mirror.
- Calibre 9.15 added an AI storytelling feature, which is either the most or the least expected place for one this week.
🤖 Robotics
- Hirebotics added line tracking and a linear rail to its cobots, pushing working range past the 68.9 inch reach that used to define the cell layout.
- Neptune Medical won FDA clearance for Triton 1, a GI robotic endoscopy system aimed at navigation and control through the whole colon.
- Icarus Robotics flew its ISS-bound robot JOY on a parabolic flight, the last major microgravity test before the system ships in early 2027.
- Nobody has a good answer yet for what happens when a humanoid reaches end of life, and the teardown turns out to be closer to surgery than to scrapping.
- Arm pulled more than 80 developers into Total Design for Physical AI plus a Robotics Capability Framework, an attempt to make robot compute stacks comparable to each other.
💻 Programming
- Mojo 1.1 opened its compiler to external contributions, which is the first release where the language’s openness claims can be checked rather than believed.
- NVIDIA introduced CUDA Rust for writing GPU kernels, putting a memory-safe language next to the one place systems programmers still accept undefined behaviour.
- Unicode 18.0 landed with 13,007 new characters, so your font stack, your column widths and your grapheme cluster assumptions all get a fresh test.
- MariaDB 13.0 went stable with new SQL surface and InnoDB changes worth reading before the next major version bump in your stack.
- Portainer 3.0 went Kubernetes-first and demoted Docker to a secondary target, which tells you where its users actually ended up.
- ZXdesk is a GEM-style desktop GUI written in assembly for the 48K ZX Spectrum, with windows, menus and applications in a machine that has no business running any of them.
⚡ Electronics
- InjectEave revives TEMPEST eavesdropping by irradiating a target at a frequency its accidental internal antennas resonate at, then reading the sidebands that nonlinear parts mix back out.
- A Sony CDX-A250 car stereo LCD got fully reverse engineered down to the LC75826W driver, with Arduino code published under MIT for anyone with a similar oddball panel.
- Avicena is showing a connectorized version of its 1 Tbps LightBundle microLED interconnect at ECOC, swapping permanent attachment for a detachable MPO interface.
- MACOM completed a 3.2T optical front end built from eight 448 Gbps PAM4 lanes, with new linear transimpedance amplifiers and a photodiode past 100 GHz.
📡 Telecom
- NewPhotonics and Tower Semiconductor moved laser-integrated photonic ICs for 800G and 1.6T engines into high-volume shipments at 200G per lane.
- Telxius is rolling Nokia ICE-X 800G ZR and ZR+ coherent pluggables across Europe, the United States and Latin America, pushing IP over DWDM further into the default design.
- Japanese operators are examining mmWave network sharing, which is the usual signal that a band’s economics are worse than its physics.
- VodafoneThree put a number on what London’s outdated planning rules cost its rollout, which is the least technical and most binding constraint in UK mobile coverage.
👨💻 Code Corner
Shoreline bandwidth density is the number today’s Big Story turns on, and it is easy to compute badly. Here is the arithmetic in one place, so you can sanity-check any interconnect claim you read this week.
"""Shoreline bandwidth density: how much traffic fits through one mm of chip edge."""
def shoreline_density(lane_rate_gbps: float, lanes: int, edge_mm: float,
duplex: bool = True) -> float:
"""Return Tb/s per mm of shoreline. Lanes are per direction if duplex."""
total_gbps = lane_rate_gbps * lanes * (2 if duplex else 1)
return total_gbps / 1000 / edge_mm
def lanes_needed(target_tbps_per_mm: float, lane_rate_gbps: float,
edge_mm: float, duplex: bool = True) -> int:
"""How many lanes per direction to hit a target density."""
total_gbps = target_tbps_per_mm * 1000 * edge_mm
per_lane = lane_rate_gbps * (2 if duplex else 1)
return -(-total_gbps // per_lane).__int__() # ceil
if __name__ == "__main__":
# The demo: 32 Gb/s NRZ lanes, massively parallel, ~1 Tb/s/mm claimed.
for lanes in (16, 32, 64):
d = shoreline_density(32, lanes, edge_mm=2.0)
print(f"{lanes:>3} lanes x 32 Gb/s over 2 mm -> {d:.2f} Tb/s/mm")
# Same target, per-lane heroics instead of width.
print("lanes for 4 Tb/s/mm @ 32 Gb/s :",
lanes_needed(4.0, 32, edge_mm=2.0))
print("lanes for 4 Tb/s/mm @ 448 Gb/s:",
lanes_needed(4.0, 448, edge_mm=2.0))
Tip
The comparison at the bottom is the whole architectural argument. Fewer, faster lanes look elegant until you price the DSP, the equalization and the joules per bit; more, slower lanes look crude until you notice they can be driven straight off a VCSEL array with almost no signal processing in the path. Always normalize competing claims to the same edge length before comparing, because vendors rarely quote the same one.
🧰 Toolbox
- RustFS 1.0: S3-compatible object storage in Rust, now generally available and worth a look if MinIO’s licence changes bothered you.
- Apio 2026-09-21: an ecosystem for open FPGA boards that hides the toolchain wrangling behind a handful of commands.
- OpenRobOps: InOrbit.AI’s reference implementation of the upcoming ISO 21423 fleet interoperability standard, useful as a spec reader even if you never run it.
- Clonezilla Live 3.3.3-37: disk imaging that now boots over HTTP and understands LUKS2, which removes two of the usual reasons to fall back to dd.
- PipeWire 1.6.9: better resampling quality in the audio layer that most Linux desktops now depend on without knowing it.
🛠️ Build of the Week (rotating)
A copper-oxide photodetector made on a kitchen stove: a light sensor built from a strip of copper, a flame and a salt water cell.
- Difficulty: Beginner
- Parts: copper sheet or tape, a gas stove or torch, salt water, a meter or a simple amplifier stage
- Why we like it: it pairs beautifully with today’s Big Story. Heat the copper until a cuprous oxide layer forms, and that layer is a semiconductor with a roughly 1.2 eV bandgap doing the same job, in principle, as the photodiode arrays in a 10 Tb/s optical engine. One costs a fraction of a cent and responds slowly; the other needs backside lenses and advanced packaging. Building the crude version is the fastest way to understand what all that packaging is actually buying.
📚 From the Blog
- Turning Pixels Into Something the AI Can Eat: episode three of the video analytics series, on decoding, preprocessing and the formats a model will actually accept.
- Building Your First Neuron From Scratch: weights, bias, activation and the nudge that makes learning happen, written out by hand.
- The Network Behind the Cameras: the natural companion to today’s Big Story, since it is the same problem one level up, moving pixels across a link without choking it.
😀 The Bot Says…
Somebody built a working ski lift to remove mice from a chicken coop, complete with 3D printed gondolas with acrylic windows, a bait-triggered trap door at the top station and an automatic release at the bottom. The mice ride down the hill in more comfort than most commuters. Whether they stay removed is, by the builder’s own admission, still an open research question.
That’s all for today! Reply and tell us: is your next scale-up domain a rack, or a row?

